IEEE ACADEMIC PROJECTS

VLSI Projects

1. a 64 bit pipeline based decimal adder using a new high speed bcd adder

2. a combined sdc sdf architecture for normal IO pipelined radix 2 fft

3. a design approach for compressor based approximate multipliers

4. aidi an adaptive image denoising fpga based ip core for real time applications

5. a low power hardware implementation of S-Box for advanced encryption standard

6. an efficient vlsi architecture of a reconfigurable pulse shaping fir interpolation filter for multistandard duc

7. an fpga implementation of a simple lossless data compression co-processor

8. a novel approach for parallel crc generation for high speed application

9. a novel floating point comparator using parallel tree structure

10. a petite and power saving design for the aes s-box

11. area effectiveandspeed optimized fused add multiply unit

12. a unified vlsi architecture for addition and multiplication in gf

13. compact implementation of sha3 512 on fpga

14. design and implementation of 32 bit unsigned multiplier Using claa and csla

15. design and implementation of radix 2 modified booth’s encoder using fpga and asic methodology

16. design of fir filter using fcsd representation

17. design of full adder subtractor using irreversible ig gate

18. design of high performance 64 bit mac unit

19. design of high performance multiply accumulate computation unit

20. design of low power and high speed carry select adder using brent kung adder

21. efficient fpga implementation of address generator for wimax einterleaver

22. enhanced memory reliability against multiple cell-upsets using decimal matrix code

23. fpga based design of low power reconfigurable router for network on chip

24. fpga based implementation-&-power analysis of parameterized walsh squences

25. hardware implementation of truncated multiplier based on multiplexer using fpga

26. implementation of 64 bit kogge stone carry select adder with zfc for efficient area

27. verification of memory transactions in axi protocol using system verilog approach

28. implementation of a high speed multiplier for high performance and low power applications

29. implementation of s-box for advanced encryption standard

30. least complex s-box and its fault detection for robust advanced encryption standard algorithm

31. low delay single symbol error correction codes based on reed solomon codes

32. low power and area efficient implementation of bcd adder on fpga

33. low power compressor based mac architecture for dsp applications

34. low power wallace tree multiplier using modified full adder

35. multiplexer based high throughput s-box for aes application

36. performance evaluation of fpga based crossbar noc architecture

37. pre encoded multipliers based on non redundant radix 4 signed digit encoding

38. recursive approach to the design of a parallel self timed adder

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