VLSI New Projects

1. A Distributed Canny Edge Detector: Algorithm and FPGA Implementation

2. A Novel Approach for Reversible Realization of 8-Bit Adder-Subtractor Circuit with Optimized Quantum Cost

3. A Novel Implementation of QPSK Modulator on FPGA

4. A Power Consumption and Area Improved Design of IIR Decimation Filters via MDT

5. An Efficient Digital Baseband Encoder for Short Range Wireless Communication Applications

6. An Efficient Implementation of a Fully Combinational Pipelined S-Box on FPGA

7. An Efficient Power Multiple Valued Look up Table For Adder Circuit Using Quaternary FPGA

8. An Ultra-Low Area and Full-Swing Output 3T XNOR Gate Using 45nm Technology

9. Analysis of Radix-2 Decimation in Time Algorithm for FPGA Co-Processors

10. Analysis of various Full-Adder Circuits in Cadence

11. Area Efficient Modified Vedic Multiplier

12. Area Optimized and High Throughput AES Algorithm based on Permutation Data Scramble Approach

13. ASIC Design of Signed and Unsigned Multipliers Using Compressors

14. Compressor Based 8x8 Bit Vedic Multiplier Using Reversible Logic

15. Design and Stability Analysis of CNTFET based SRAM Cell

16. Design of a Lifting Based Discrete Wavelet Transform Using Flipping Method for Images

17. Design Of Basic Sequential Circuits Using Reversible Logic

18. Design of High Performance 8-bit Vedic Multiplier

19. Design of high speed multiplier using Modified Booth Algorithm with hybrid carry look-ahead adder

20. Exploiting Adder Compressors for Power-Efficient 2-D Approximate DCT Realization

21. FinFET Based 4-BIT Input XOR/XNOR Logic Circuit

22. FPGA for Multi Input Multi Output Orthogonal Frequency Division Multiplexing

23. FPGA Implementation of an Optimized NLMS Algorithm

24. GDI Implementation of Low Power Modified Booth Multiplier

25. High Performance VLSI Architecture for 3-D Discrete Wavelet Transform

26. High speed vedic Multipler for image processing using FPGA

27. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

28. Implementation of a Fast Hybrid CORDIC Architecture

29. Implementation of Arithmatic Logic Unit using GDI Technique

30. Low complexity and area efficient reconfigurable multimode interleaver address generator for multistandard radios

31. Low power encoder for flash ADC Architecture

32. Low Power Multiplier using Algorithmic Noise Tolerant Architecture

33. Mapping of Five input Wallace tree using Cadence Tool for Low Power, Low area and High Speed

34. Modeling of Adders using CMOS and GDI Logic for Multiplier Applications

35. NEDA Based Hybrid Architecture for DCT - HWT

36. Performance Analysis of Low Power 6T SRAM Cell in 180nm and 90nm

37. Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs

38. Transistor level implementation of An 8-Bit Multiplier using Vedic Mathamatican in 180nm Technology

39. Verification of a Digital Video Broadcasting – Satellite to Handheld (DVB-SH) IP Using UVM

40. Verilog Implementation of Adaptive Compression of RGB images at low bit rates

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